Several trends continue to be present in the semiconductor and electronics industry. Devices continue to be made smaller, faster and require less power while operating. One reason for this ongoing trend is that personal electronic devices are being fabricated that are designed to be smaller, and yet at the same time, packaged with greater memory capability. For example, cellular phones, personal computing devices, recorders, and personal sound systems are getting smaller while the memory capability, speed and computational power are expanding. In light of these trends, there is an ever increasing demand in the semi-conductor industry for smaller and faster transistors to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor marketplace there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., submicron levels) on semiconductor wafers. In order to accomplish these higher densities, smaller feature sizes and reduced separation between features, more precise feature shapes are required to be placed on the small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, the diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges), and the like. The scaling-down of integrated circuit dimensions results in faster circuit performance and/or switching speeds, and can lead to higher effective yields in IC fabrication by providing more circuits on a silicon die and/or more silicon die per semiconductor wafer.
The process of manufacturing integrated circuits involves numerous process steps, during which hundreds/thousands of copies of an integrated circuit are formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. A typical process of manufacturing these active areas in a metal-oxide-semiconductor-field-effect-transistor (MOSFET) requires ion implanting of the source and drain. With devices becoming smaller and smaller the current approach within the industry has been to implant ions shallowly so that the lateral and vertical junctions are shallow, as well.
However, short channel effects have to be minimized as the industry scales down the memory cells. A common known problem within the industry is that as one cell is programmed, the cell next to it is erroneously programmed as well, commonly referred to as “program disturb”. Although not totally understood, one possibility is that electrons or holes are migrating around to the other side of the device and programming the cell.
Accordingly, it would be desirable to allow transistors to be scaled down while preventing erroneous or undesired programming of the cell.